1. Field of the Invention
The present invention relates to an integrated circuit built-in type supply power (power-on) delay circuit, and in particular, to an improved integrated circuit built-in type supply power delay circuit which is capable of supplying a stable power by implementing a regeneration operation based on a delay and negative feedback by a current discharging in a capacitance or MOS capacitance.
2. Description of the Conventional Art
Conventionally, the integrated circuit built-in type power supply (power-on) delay circuit is a circuit for delaying a power supply for a predetermined time when an unstable power is supplied to the circuit, and then supplying a stable electric power to each element of the circuit.
In particular, a bias circuit which generates an accurate reference voltage and current and a power supply-sensitive circuit need a stable electric power supply. Generally, since the power supply greatly affects the stability of the entire circuit, much study has been intensively performed on the method of stabilizing the supply power.
As one of the conventional methods, there is a method of using a control logic such as a flip-flop for charging/discharging a capacitor in a supply power reset circuit and checking the operational state by using a comparator. In addition, there is a sequence power delay circuit which includes a complicated time delay rectifier and a relay unit with respect to an alternating current (AC).
However, the conventional supply power delay circuit has a complicated construction, and when additional devices are used in an electronic system, the supply power delay circuit is disposed in an integrated circuit, for thus complicating the configuration of the circuit.